1. Field of Disclosure
The present disclosure generally relates to a memory apparatus, and more particularly to a signal delay circuit for generating a delayed column select signal with wider pulse to provide to the memory apparatus.
2. Description of Prior Art
For a memory apparatus in prior art, a column select signal must be provided to a sense amplifier in the memory apparatus when a writing operation of the memory apparatus is executing. The column select signal is used to turn on a switch pair for transmitting data and inverted data to the sense amplifier. It is important that the column select signal must have a proper pulse width to insure the proper data transmitted to the sense amplifier.
Referring to the FIG. 1A, FIG. 1A is a circuit diagram of a signal delay circuit 100 in prior art. The signal delay circuit 100 includes an inverter IV1, an inverter IV2 and a capacitor C1. The inverter IV1 has an input terminal for receiving a column select signal CS, and an output terminal coupled to the capacitor C1 and an input terminal of the inverter IV2. The capacitor C1 is coupled between the output terminal of the inverter IV1 and a ground voltage. An output the inverter IV1 generates a delayed column select signal CSd.
Referring to the FIG. 1B and FIG. 1A, wherein FIG. 1B is a memory apparatus 10 in prior art. The memory apparatus 10 includes the signal delay circuit 100, a sense amplifier 11, switches SW1 and SW2 and data-in drivers DINV1 and DINV2. There is a problem when the intended written data has the opposite polarity of the sens amplifier 11 polarity where data “0” is the opposite polarity of the data “1” or vis versa intended to be written into a memory cell in the memory apparatus 10, and the P-type transistors MP (MOS transistors) in the sense amplifier 11 which coupled to the signal delay circuit 100 is stronger (faster) device, and the N-type transistors (MOS transistors) in the data-in drivers DINV1, DINV2 and SW1, SW2 are weaker (slower) devices. The weaker drivers (N-type transistors in the data-in drivers DINV1, DINV2) and SW1, SW2 (which are N-Type) have to fight the strong device (P-type transistor MP in the sense amplifier 11) to pull a data line coupled to the sense amplifier to opposite digital data. Therefore, in this case, the delayed column select signal CSd with a longer pulse width is needed. However, in prior art, the pulse width of the delayed column select signal CSd cannot be optimized according to the process variation, such as that, the efficiency of the memory apparatus is reduced correspondingly.